Low Temperature Poly-Silicon (LTPS) process is usually employed in TFT array assembly portion of an AMOLED. Qualities of the TFTs and the array assembly including the TFTs will decide final display quality of the AMOLED.
In processes for manufacturing an AMOLED_LTPS TFT (see FIGS. 1˜2), using a photoresist pattern 122 as a mask, a part of a gate metal layer and a gate insulating layer is etched, and thus a gate line (not shown), a gate electrode 120′ and e.g. a silicon nitride foot 118′ below the gate electrode are formed. At this time, a lower insulating layer such as a silicon oxide layer 116′ may also be etched, which results in a silicon oxide loss (as indicated by the circle in FIG. 1). As a result, there exists difference in dopant implantation profiles of a source region S and a drain region D, which therefore results in difference in electrical property (such as Ion, Ioff, Vth, mobility, etc.) of final products.
Thus, a method for reducing the insulating layer loss when manufacturing a TFT is needed.
The above information disclosed in the background portion is only for purpose of enhancing understanding of the background of the present disclosure, and thus it may include information which does not constitute prior art known to one of ordinary skill in this art.